How to Reverse Engineer a PCB Board: Complete Step-by-Step Guide

This is a real project walkthrough — not a theoretical guide.

The board: a 500W sine wave inverter, 2-layer PCB, with no

surviving design files.

What we started with: the physical board, a camera, and a

flatbed scanner.

What we ended with: a complete verified BOM (69 components

identified), a fully reconstructed schematic in Altium Designer,

and production-ready Gerber files.

This guide documents exactly what we did, step by step — with

real photos, real scans, and real files from this project.

Whether you need to reverse engineer a legacy industrial board,

recreate a discontinued product, or simply understand how an

existing circuit works, this process applies.

Tools required:

- High-resolution camera or flatbed scanner (1200 DPI recommended)

- Digital calipers

- Multimeter with continuity mode

- LCR meter (for passive component measurement)

- Soldering iron + desoldering pump

Software:

- KiCad (free) or Altium Designer

- Excel / Google Sheets for BOM logging

Components reference sources:

- Mouser, Digi-Key, LCSC

For multilayer boards (4L+):

- X-ray imaging equipment OR

- Abrasive planarization setup (destructive method, requires 2-3 sample boards)

This is your single most important step. Everything that follows

depends on the quality of your documentation here.

For this project, we started with a 500W sine wave inverter board.

No schematic, no BOM, no fabrication notes — just the physical board.

What to do:

1. Photograph BOTH sides of the board at high resolution (minimum

12MP). Use a flat, well-lit surface with no shadows across traces.

2. Use a flatbed scanner if available. 1200 DPI gives enough

resolution to measure trace widths later.

3. Document every component location BEFORE removing anything.

Number each IC, connector, and large component on your photo.

4. Measure overall board dimensions and mounting hole positions

with digital calipers. Record: Length × Width × Thickness.

5. Note any markings on the board: revision numbers, date codes,

manufacturer stamps, UL/CE marks.

6. Check the board edge under strong light — count the visible

copper layers in the cross-section. This tells you the layer

count before you commit to any imaging method.

For this inverter board: 215mm × 90mm, 2-layer, no revision

markings, date code worn off.

Pro tip: Print one copy of the top-side photo and use it as your

working map. Cross off each component as you identify it in Step 2.

Common mistake: Skipping photography and going straight to

component identification. If you lose track of a component's

original position, you cannot recover it.

Every IC, resistor, capacitor, connector, and module must be

identified and logged into a Bill of Materials (BOM).

For this inverter board, we identified 69 unique component types

across 130+ total placements — all SMD and THT mixed technology.

Process:

1. Start with ICs and active components first — they define the

board's function. Read the part number printed on the package

and search the manufacturer datasheet.

Key ICs identified on this board:

- XL7015E1 (TO252-5) — DC-DC buck controller

- SX1308 (SOT23-6) — Boost converter

- GS8332-SR (SOP-8) × 2 — Gate driver ICs

- NCE6008AS (SOP-8) × 2 — N-channel MOSFETs

- LM321MFX (SOT23-5) × 3 — Single op-amp

- EG1163S (SOP-16) — PWM controller

2. For passive components, measure values with a multimeter or

LCR meter. SMD resistors have a printed code:

- "01C" = 10KΩ

- "01D" = 100KΩ

- "512" = 5.1KΩ

3. For power components, record package and voltage/current rating:

- STP110N8F6 (TO220) — N-channel MOSFET, main switching device

- NCE82H140 (TO220) × 2 — N-channel MOSFET

- SS1150 / S10C100D — Schottky diodes

- SMBJ75A / SMBJ6.5A — TVS protection diodes

4. Log everything into a spreadsheet with these columns:

No. / Component Name / Marking / Part Number / Package /

Manufacturer / Mount Type / Reference Designators / Qty

5. Cross-reference against datasheets to confirm pinout before

schematic reconstruction in Step 4.

For worn or unreadable markings on old boards: infer the part

from circuit position, nearby components, and power rail voltages.

On this board, three components had partially worn markings —

identified by tracing gate driver signal paths.

The completed BOM for this project is attached below as a

downloadable Excel file.

For 2-layer boards, your photos from Step 1 are sufficient.

Skip directly to Step 4.

For 4-layer and above: you cannot see internal layers without

either X-ray imaging or physical cross-sectioning. Do not skip

this step — guessing internal routing will produce a board that

looks correct but fails electrically.

This inverter board is 2-layer, so we used flatbed scanning

to capture both copper layers cleanly after chemical stripping

of the soldermask.

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Two imaging methods for multilayer boards:

Option A — Flatbed Scanning (2-layer boards)

After careful soldermask removal, scan each side at 1200 DPI.

The scan captures:

- Top copper layer (component side)

- Bottom copper layer (solder side)

- Via locations and drill pattern

Four scan outputs from this project:

- T.jpg — Top copper layer

- TL.jpg — Top layer with silkscreen overlay

- B.jpg — Bottom copper layer

- BL.jpg — Bottom layer with silkscreen overlay

These become your trace routing reference in Step 5.

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Option B — X-ray Imaging (4-layer+, non-destructive)

X-ray maps internal vias, buried vias, and power/ground plane

structures without damaging the board. Required when:

- Client has only one sample board

- Board must remain functional after reverse engineering

- Layer count is 4 or more

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Option C — Abrasive Planarization (4-layer+, destructive)

Progressive mechanical grinding exposes each layer for scanning.

Key parameters from our process:

- Minimum 2 sample boards required (1 reference, 1 to destroy)

- For 6-layer boards with unknown stackup: use 3 boards

- Maintain consistent grinding depth across the entire panel

- A tilted board ruins the cross-section — fixturing is critical

The real challenge is not the grinding itself. It is keeping the

board perfectly flat and removing material at a consistent depth

per pass. Even 0.05mm tilt across the board width will cause you

to lose one layer's traces on one side before the other side is

fully exposed.

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Layer count determination (before committing to any method):

Hold the board edge up to a strong backlight. Count the visible

copper layers in the PCB cross-section. Confirm against the board

thickness

With your BOM complete and layer scans in hand, you now rebuild

the schematic from scratch. This is where engineering judgment

matters most — tools can trace copper, but only experience tells

you whether what you're looking at is a filter, a feedback loop,

or a protection circuit.

Software used for this project: Altium Designer

Alternative: KiCad (free, works well for this workflow)

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Process:

1. Create a new schematic and place all components from your BOM.

Use the correct schematic symbols — do not use generic boxes.

Correct symbols make net tracing dramatically faster.

2. Start with the power architecture first:

- Identify VIN, VOUT, VCC rails

- Trace the main power path from input to output

- Mark GND net on every ground connection before touching

signal nets

For this inverter board, the power path is:

VIN (DC input) → Q1 STP110N8F6 (main switch) → L3 inductor

→ output stage → JP1/JP5 terminals (AC output)

3. Identify functional blocks and reconstruct block by block:

- DC-DC supply section (XL7015E1 buck + SX1308 boost)

- Gate driver section (GS8332-SR × 2 driving Q3/Q4/Q7)

- PWM controller section (EG1163S)

- Feedback and protection (LM321MFX op-amps × 3)

- Input protection (TVS diodes, resettable fuse FU1)

4. Trace each net using your scan images as reference.

Use multimeter continuity mode to verify any connection

that is unclear in the scan — probe directly on the board.

Never guess a net connection.

5. Cross-check every IC pin against its datasheet application

circuit. Any pin connection that deviates from the datasheet

typical application is either:

- An intentional design choice (document it)

- A misread trace (re-probe it)

6. Build net labels consistently:

VIN, VOUT, VCC, VCC1, GND, 3V, 3.6V, SDHIN, SDLIN,

HO, LO, VS, VB, EN, FR, ERRO, REF5V, SS, CP

(actual net names from this project's schematic)

7. Once all nets are connected, run ERC (Electrical Rules Check).

Fix all errors before moving to layout.

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Common mistake: Relying on autotracing software without

verification. Automated tools regularly misread damaged traces,

silkscreen overlap, and tented vias. Every net must be

manually confirmed.

For this project, schematic reconstruction took approximately

14 hours across 2 days for a 2-layer mixed-technology board

with 69 component types.

With a verified schematic, you now recreate the physical PCB

layout. The goal is not just a working board — it is a board

that can be manufactured reliably and repeatedly.

Software used for this project: Altium Designer

The reconstructed layout file is: 14876 A289PCB se.pcb

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Process:

1. Set up board outline

Match the original dimensions exactly.

This inverter board: 215mm × 90mm, rectangular.

Import or draw the board edge on the Mechanical layer.

Place mounting holes at measured positions from Step 1.

2. Import netlist from schematic

In Altium: Design → Import Changes From schematic.

All 69 component footprints load with their net connections.

Verify zero errors in the Engineering Change Order (ECO)

before proceeding.

3. Place components matching original positions

Use your scaled scan images as an underlay reference:

- In Altium: Place → Graphics → load T.jpg as background

- Scale the image to match board dimensions

- Place each component over its original position

Placement priority for this board:

- Power components first: Q1, Q3, Q4, Q7 (TO220 MOSFETs)

- Large capacitors: CP3, CP6 (electrolytic, D13-16mm)

- ICs: EG1163S, GS8332-SR, XL7015E1

- Passives last: resistors and small capacitors

4. Route traces matching original routing

Match original trace widths:

- Power traces (VIN, VOUT, gate drive): 2.0mm - 3.0mm+

- Signal traces: 0.2mm - 0.5mm

- Use Pour (copper fill) for GND on both layers

5. Recreate copper pours

Top layer: GND pour covering non-signal areas

Bottom layer: GND pour + power routing

Set clearance rules before pouring:

- Trace to pour: 0.3mm minimum

- Via to pour: 0.25mm minimum

6. Thermal relief note

The original board had NO thermal relief on GND connections

— a common characteristic of pre-CAD era designs.

For the reconstructed layout, we added standard thermal

relief (4-spoke, 0.3mm spoke width) on all THT component

pads connected to GND planes.

This makes the new board significantly easier to rework

and solder compared to the original.

7. Run DRC (Design Rule Check)

Fix all violations before generating output.

Zero errors required before Gerber export.

8. Run DFM Review

Key checks for this board:

- Minimum trace/space: 0.15mm / 0.15mm ✅

- Via drill size: 0.3mm minimum ✅

- Copper to board edge: 0.3mm minimum ✅

- Soldermask expansion: 0.05mm per side ✅

- TO220 pad size: verified against IPC-7351 ✅

9. Generate Gerber output files

Required files for fabrication:

- GTL — Top copper layer

- GBL — Bottom copper layer

- GTS — Top soldermask

- GBS — Bottom soldermask

- GTO — Top silkscreen

A reconstructed board that looks correct on screen means nothing

until it performs identically to the original under real operating

conditions. No assumptions. No "close enough."

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Pre-power checklist (do this before connecting any power):

1. Continuity check — GND to VIN

Measure resistance between GND and VIN terminals.

Should read open circuit (>1MΩ).

A low reading means a short — do not power on.

2. Visual inspection under magnification

Check for:

- Solder bridges on IC pads (especially SOP-8 and SOP-16)

- Cold joints on TO220 power devices

- Missing components

- Reversed polarity on electrolytic capacitors (CP3, CP6)

- TVS diode orientation (D4, D6, D9)

3. Verify electrolytic capacitor polarity

CP3: 1000uF 80V — longest lead = positive

CP6: 470uF 80V — longest lead = positive

CP1: 22uF 100V — longest lead = positive

Wrong polarity = immediate failure on power-up.

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Power-on sequence:

Step 1 — Apply VIN with current limiting

Use a bench power supply with current limit set to 100mA.

Slowly raise voltage from 0V to rated VIN.

Watch for current draw — should stay under 50mA at no load.

Step 2 — Verify internal power rails

Measure these test points before applying full load:

- VCC: expected ~15V (gate drive supply)

- VCC1: expected ~15V

- 3V rail: expected 3.0V ±0.1V

- 3.6V rail: expected 3.6V ±0.1V

- 5V REF: expected 5.0V ±0.05V

Any rail out of spec: stop, trace back to its source IC.

Step 3 — Verify PWM signal

Probe EG1163S (U6) output pins with oscilloscope.

You should see a PWM waveform at the expected switching

frequency before gate drive signals appear.

Step 4 — Apply full rated load

Once all rails verified, connect rated load.

For this 500W inverter: resistive load bank at rated output.

Monitor:

- Output voltage and waveform shape (sine wave)

- Input current draw

- Temperature of Q1, Q3, Q4, Q7 after 10 minutes

Step 5 — Compare against original board behavior

Run both boards under identical conditions.

Output waveform, efficiency, and thermal profile must match.

Any deviation requires root cause analysis before production.

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First-article failure: most common causes

If the board fails verification, these are the most likely causes

in order of frequency:

1. Missed net connection in schematic (wrong pin traced)

2. Wrong passive component value (misread SMD code)

3. IC orientation error (pin 1 marking misread)

4. Copper pour isolation issue (GND shorting a signal net)

5. Via drill miss (net open due to undrilled via in Gerber)

Return to Step 4 for causes 1-2.

Return to Step 5 for causes 3-5.

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Final documentation package

Once functional verification passes, you have a complete

reverse engineering deliverable:

✅ Verified BOM — 69 components, all sourced from current

distributors (Mouser / Digi-Key / LCSC)

✅ Reconstructed schematic — Altium .SchDoc + PDF export

✅ Verified PCB layout — Altium .pcb + Gerber files

✅ Fabrication specification — layer stackup, materials,

surface finish, tolerances

✅ Test report — rail voltages, waveform captures,

thermal measurements

This documentation set is also the right moment to establish

formal version control. The reason you needed reverse engineering

in the first place was often because version control did not

exist the first time around. Use Git for Gerbers, or at minimum

a structured folder with revision numbering.

Do not repeat the same problem on the next design.

You've now seen the complete process — from photographing a

board with no surviving files to a verified, production-ready

documentation package.

For this 500W inverter project, the full process took:

- Photography and documentation: 2 hours

- Component identification and BOM: 6 hours

- Layer scanning and imaging: 3 hours

- Schematic reconstruction: 14 hours

- PCB layout recreation: 10 hours

- Verification and documentation: 4 hours

- Total: approximately 39 hours for a 2-layer,

69-component mixed-technology board

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DIY reverse engineering works well when:

✅ The board is 1–2 layers

✅ Component count is under 50

✅ You have access to all required tools

✅ Timeline is flexible

✅ It is a personal or hobbyist project

Consider professional reverse engineering when:

⚠️ The board is 4 layers or more

(X-ray equipment required — not practical for one-off DIY)

⚠️ You have only one sample board

(Destructive methods require sacrificial boards)

⚠️ The project is going into production

(Liability, documentation standards, and traceability matter)

⚠️ Turnaround time is critical

(Professional teams run schematic and layout in parallel)

⚠️ The board contains proprietary ICs with no public datasheet

(Requires specialized identification techniques)

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Legal note:

PCB reverse engineering is legal when:

- You own the board

- The original manufacturer no longer supports the product

- You are recreating for maintenance or obsolescence management

- You have explicit authorization from the IP owner

PCB reverse engineering is NOT legal when:

- The purpose is to copy a competitor's product

- You are circumventing active IP protection

- The board contains export-controlled technology

When in doubt, consult a lawyer before starting.

We only take on projects where the client owns the board

and the original manufacturer is no longer available.

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If you found this guide useful, the full written version

with additional detail on tools, DFM considerations, and

multilayer methods is available here:

👉 Full guide: https://tjhxpcb.com/blog/reverse-engineering-a-pcb-board/

For professional PCB reverse engineering, fabrication,

or assembly services:

👉 https://tjhxpcb.com/pcb-reverse-engineering/

Questions about a specific board?

📧 contact@tjhxpcb.com

📱 WhatsApp: +86 150 2256 3520