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-- Company: 
-- Engineer: 
-- 
-- Create Date: 06/03/2018 08:30:23 PM
-- Design Name: 
-- Module Name: bpmcreator - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bpmcreator is
    Port ( clk : in STD_LOGIC;
           truebpm : in integer;
           sled : out std_logic;
           enable : out STD_LOGIC);
end bpmcreator;

architecture Behavioral of bpmcreator is
component clk_div_bpmcr is
        Port(clk : in std_logic;
             rate : in integer;
             sclk : out std_logic);
end component;

signal sclk : std_logic;
signal isenabled : std_logic;

begin
clkdiv: clk_div_bpmcr
        Port map(clk => clk,
                 rate => truebpm,
                 sclk => sclk);
    sled <= sclk;
    process(sclk)
    variable ct : integer := 5;
    begin
        if rising_edge(sclk) then
            if ct = 5 then
                ct := 0;
                isenabled <= '1';
            else
                ct := ct + 1;
                isenabled <= '0';
            end if;
            enable <= isenabled;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
-----------------------------------------------------------------------
-- Module to divide the clock 
-----------------------------------------------------------------------
entity clk_div_bpmcr is
    Port (  clk : in std_logic;
            rate : in integer;
           sclk : out std_logic);
end clk_div_bpmcr;

architecture my_clk_div of clk_div_bpmcr is
   constant max_count : integer := rate * 8;  
   signal tmp_clk : std_logic := '0'; 
begin
   my_div: process (clk,tmp_clk)              
      variable div_cnt : integer := 0;   
   begin
      if (rising_edge(clk)) then   
         if (div_cnt >= MAX_COUNT) then 
            tmp_clk <= not tmp_clk; 
            div_cnt := 0; 
         else
            div_cnt := div_cnt + 1; 
         end if; 
      end if; 
      sclk <= tmp_clk; 
   end process my_div; 
end my_clk_div;