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-- Company: 
-- Engineer: 
-- 
-- Create Date: 05/30/2018 02:06:15 PM
-- Design Name: 
-- Module Name: freqGen - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity freqGen is
    Port ( sw : in STD_LOGIC_vector(7 downto 0);
           freq : out integer;
           oct : in std_logic_vector(1 downto 0));
end freqGen;

architecture Behavioral of freqGen is

constant C : unsigned(20 downto 0) := "101110101001111110010";
constant D : unsigned(20 downto 0) := "101001100100001101011";
constant E : unsigned(20 downto 0) := "100101000010000000101";
constant F : unsigned(20 downto 0) := "100010111101000000000";
constant G : unsigned(20 downto 0) := "011111001000111111000";
constant A : unsigned(20 downto 0) := "011011101111100100011";
constant B : unsigned(20 downto 0) := "011000101101110111001";
constant C2 : unsigned(20 downto 0) := "010111010101000110100";

component shifter is
    Port(bitstring : in unsigned(20 downto 0);
         amt : in std_logic_vector(1 downto 0);
         shifted : out unsigned(31 downto 0));
end component;

signal note : unsigned(20 downto 0);
signal tofrq : unsigned(31 downto 0);
begin
    shiftright: shifter
        Port map(bitstring => note,
                 amt => oct,
                 shifted => tofrq);
    process(sw) begin
        case(sw) is
            when "10000000" =>
                note <= C;
            when "01000000" =>
                note <= D;
            when "00100000" =>
                note <= E;
            when "00010000" =>
                note <= F;
            when "00001000" =>
                note <= G;
            when "00000100" =>
                note <= A;
            when "00000010" =>
                note <= B;
            when "00000001" =>
                note <= C2;
            when others =>
                note <= "000000000000000000000";
        end case;
        freq <= to_integer(tofrq);
    end process;


end Behavioral;