//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 //Date : Thu Nov 22 13:42:31 2018 //Host : FEYNMAN running 64-bit major release (build 9200) //Command : generate_target hdmi_wrapper.bd //Design : hdmi_wrapper //Purpose : IP block netlist //-------------------------------------------------------------------------------- `timescale 1 ps / 1 ps module hdmi_wrapper (DDC_scl_io, DDC_sda_io, DDR_addr, DDR_ba, DDR_cas_n, DDR_ck_n, DDR_ck_p, DDR_cke, DDR_cs_n, DDR_dm, DDR_dq, DDR_dqs_n, DDR_dqs_p, DDR_odt, DDR_ras_n, DDR_reset_n, DDR_we_n, FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp, FIXED_IO_mio, FIXED_IO_ps_clk, FIXED_IO_ps_porb, FIXED_IO_ps_srstb, HDMI_rx_hpd, HDMI_tx_hpd, TMDS_Clk_n, TMDS_Clk_n_1, TMDS_Clk_p, TMDS_Clk_p_1, TMDS_Data_n, TMDS_Data_n_1, TMDS_Data_p, TMDS_Data_p_1, aPixelClkLckd, clk, LED0, LED1, LED2); inout DDC_scl_io; inout DDC_sda_io; inout [14:0]DDR_addr; inout [2:0]DDR_ba; inout DDR_cas_n; inout DDR_ck_n; inout DDR_ck_p; inout DDR_cke; inout DDR_cs_n; inout [3:0]DDR_dm; inout [31:0]DDR_dq; inout [3:0]DDR_dqs_n; inout [3:0]DDR_dqs_p; inout DDR_odt; inout DDR_ras_n; inout DDR_reset_n; inout DDR_we_n; inout FIXED_IO_ddr_vrn; inout FIXED_IO_ddr_vrp; inout [53:0]FIXED_IO_mio; inout FIXED_IO_ps_clk; inout FIXED_IO_ps_porb; inout FIXED_IO_ps_srstb; output HDMI_rx_hpd; input HDMI_tx_hpd; input TMDS_Clk_n; output TMDS_Clk_n_1; input TMDS_Clk_p; output TMDS_Clk_p_1; input [2:0]TMDS_Data_n; output [2:0]TMDS_Data_n_1; input [2:0]TMDS_Data_p; output [2:0]TMDS_Data_p_1; output aPixelClkLckd; input clk; output LED0; output LED1; output LED2; wire DDC_scl_i; wire DDC_scl_io; wire DDC_scl_o; wire DDC_scl_t; wire DDC_sda_i; wire DDC_sda_io; wire DDC_sda_o; wire DDC_sda_t; wire [14:0]DDR_addr; wire [2:0]DDR_ba; wire DDR_cas_n; wire DDR_ck_n; wire DDR_ck_p; wire DDR_cke; wire DDR_cs_n; wire [3:0]DDR_dm; wire [31:0]DDR_dq; wire [3:0]DDR_dqs_n; wire [3:0]DDR_dqs_p; wire DDR_odt; wire DDR_ras_n; wire DDR_reset_n; wire DDR_we_n; wire FIXED_IO_ddr_vrn; wire FIXED_IO_ddr_vrp; wire [53:0]FIXED_IO_mio; wire FIXED_IO_ps_clk; wire FIXED_IO_ps_porb; wire FIXED_IO_ps_srstb; wire HDMI_rx_hpd; wire HDMI_tx_hpd; wire TMDS_Clk_n; wire TMDS_Clk_n_1; wire TMDS_Clk_p; wire TMDS_Clk_p_1; wire [2:0]TMDS_Data_n; wire [2:0]TMDS_Data_n_1; wire [2:0]TMDS_Data_p; wire [2:0]TMDS_Data_p_1; wire aPixelClkLckd; wire LED0; wire LED1; wire LED2; reg [27:0]pixel_cnt; reg pixel_beat; assign LED0 = pixel_beat; // // Generate Pixel Beat // always @(posedge clk) begin if (aPixelClkLckd == 0) begin pixel_cnt <= 0; pixel_beat <= 0; end else if (pixel_cnt[25] == 1) begin pixel_cnt <= 0; pixel_beat <= ~pixel_beat; end else begin pixel_cnt <= pixel_cnt + 1'b1; end end IOBUF DDC_scl_iobuf (.I(DDC_scl_o), .IO(DDC_scl_io), .O(DDC_scl_i), .T(DDC_scl_t)); IOBUF DDC_sda_iobuf (.I(DDC_sda_o), .IO(DDC_sda_io), .O(DDC_sda_i), .T(DDC_sda_t)); hdmi hdmi_i (.DDC_scl_i(DDC_scl_i), .DDC_scl_o(DDC_scl_o), .DDC_scl_t(DDC_scl_t), .DDC_sda_i(DDC_sda_i), .DDC_sda_o(DDC_sda_o), .DDC_sda_t(DDC_sda_t), .DDR_addr(DDR_addr), .DDR_ba(DDR_ba), .DDR_cas_n(DDR_cas_n), .DDR_ck_n(DDR_ck_n), .DDR_ck_p(DDR_ck_p), .DDR_cke(DDR_cke), .DDR_cs_n(DDR_cs_n), .DDR_dm(DDR_dm), .DDR_dq(DDR_dq), .DDR_dqs_n(DDR_dqs_n), .DDR_dqs_p(DDR_dqs_p), .DDR_odt(DDR_odt), .DDR_ras_n(DDR_ras_n), .DDR_reset_n(DDR_reset_n), .DDR_we_n(DDR_we_n), .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), .FIXED_IO_mio(FIXED_IO_mio), .FIXED_IO_ps_clk(FIXED_IO_ps_clk), .FIXED_IO_ps_porb(FIXED_IO_ps_porb), .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), .HDMI_rx_hpd(HDMI_rx_hpd), .HDMI_tx_hpd(HDMI_tx_hpd), .TMDS_Clk_n(TMDS_Clk_n), .TMDS_Clk_n_1(TMDS_Clk_n_1), .TMDS_Clk_p(TMDS_Clk_p), .TMDS_Clk_p_1(TMDS_Clk_p_1), .TMDS_Data_n(TMDS_Data_n), .TMDS_Data_n_1(TMDS_Data_n_1), .TMDS_Data_p(TMDS_Data_p), .TMDS_Data_p_1(TMDS_Data_p_1), .aPixelClkLckd(aPixelClkLckd), .LED1(LED1), .LED2(LED2)); endmodule