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-- Company: 
-- Engineer: 
-- 
-- Create Date: 06/05/2018 07:16:12 PM
-- Design Name: 
-- Module Name: shifter - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shifter is
    Port ( bitstring : in unsigned(20 downto 0);
           amt : in STD_LOGIC_vector(1 downto 0);
           shifted : out unsigned(31 downto 0));
end shifter;

architecture Behavioral of shifter is

begin
    with amt select
            shifted <= "00000000000" & bitstring when "00",
                       "000000000000" & bitstring(20 downto 1) when "01",
                       "0000000000000" & bitstring(20 downto 2) when "10", 
                       "00000000000000" & bitstring(20 downto 3) when "11",
                       "00000000000" & bitstring when others;

end Behavioral;